VLSI Digital Signal Processing Systems: Design and Implementation

F.1    INTRODUCTION

A special case of high-level synthesis is the synthesis of bit-serial architectures. In bit-serial systems, no allocation is performed, i.e., each algorithm operation is mapped to a unique bit-serial functional unit. In bit-serial architectures, a complete word is not computed in a single clock but is computed over a series of clock cycles. Therefore the task of scheduling bit-serial architectures is important to ensure the inputs and outputs are synchronized correctly. This appendix presents an algorithm for optimal resource-constrained scheduling of bit-serial architectures. In this algorithm, it is assumed that a one-to-one mapping of operations to hardware functional units exist and that there is no need for functional unit allocation. The goal of the bit-serial scheduling algorithm is to assign the operations to time steps while minimizing the number of required synchronizing registers.

A bit-serial architecture is often represented by the timing model shown in Fig. F.1 and is used in the bit-serial scheduling algorithm. This model represents the necessary relative timing of the inputs and outputs of a bit-serial operator. In Fig. F.1 a functional unit (or operator) i scheduled to begin computations at time step T_i expects to see the first bit of input x₁ at time T_i + t(x₁), input x₂ at time T_i + t(x₂), …, and input x_m at time T_i + t(x_m). Operator i produces the first bit of output y₁ at time T_i + t(y₁), output y₂ at time T_i + t(y₂), …, and output y_n at ...