O'Reilly logo

VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

E.2    MULTIPLEXER-BASED FAST BINARY ADDERS

This section considers implementation of Manchester, carry-select, and carry- look-ahead based fast binary adders using multiplexers only.

image

Fig. E.1    Block diagram of a Manchester adder.

E.2.1    Multiplexer-Based Manchester Adder

In a binary addition, a carry ci can be either generated at stage i or propagated from the preceding stage. A carry is generated at stage i if xi and yi are both 1, and a carry is propagated from stage i−1 to stage i+1 if only one of the operands (xi, yi) is 1 but not both [1]. Let gi and pi denote the carry generation and the propagation at stage i. These can be computed as:

image

image

where ⊕ denotes XOR operation. The carry ci+1 and the sum si at each stage are computed by:

image

image

Hence, an adder based on this principle consists of 3 sequential stages:

  • PG-logic: compute all pairs of (gi, pi) based on (E.1) and (E.2) in parallel;
  • Carry-generator: computes all carries ci+1 based on (E.3);
  • Sum-generator: computes all sum bits

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required