VLSI Digital Signal Processing Systems: Design and Implementation

7.1    INTRODUCTION

Systolic architectures (also referred to as systolic arrays) represent a network of processing elements (PEs) that rhythmically compute and pass data through the system. These PEs regularly pump data in and out such that a regular flow of data is maintained [1],[2]. As a result, systolic systems feature modularity and regularity, which are important properties for VLSI design. The systolic array may be used as a coprocessor in combination with a host computer where the data samples received from the host computer pass through the PEs and the final result is returned to the host computer (see Fig. 7.1). This operation is analogous to the flow of blood through the heart, thus the name “systolic”.

Typically, all the PEs in a systolic array are uniform and fully pipelined, i.e., all communicating edges among the PEs contain delay elements, and the whole system usually contains only local interconnections [3]. However, some relaxations have been introduced to increase the utility of systolic arrays. These relaxations include use of not only local but also neighbor (near, but not nearest) interconnections, use of data broadcast operations, and use of different PEs in the system, especially at the boundaries. With these relaxations, a family of modular, regular, and efficient data-driven array architectures can be designed for DSP applications.

This chapter presents the systolic architecture design methodology where many systolic architectures can be designed for any ...