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VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

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6.1    INTRODUCTION

In synthesizing DSP architectures, it is important to minimize the silicon area of the integrated circuits, which is achieved by reducing the number of functional units (such as adders and multipliers), registers, multiplexers, and interconnection wires. The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations (such as addition operations) are time-multiplexed to a single functional unit (such as a pipelined adder) [1],[2]. By executing multiple algorithm operations on a single functional unit, the number of functional units in the implementation is reduced, resulting in an integrated circuit with low silicon area. Although folding technique can be used for synthesis of DSP architectures that can be operated using single or multiple clocks, this chapter only addresses synthesis of circuits operated by a single clock.

Fig. 6.1 shows an example of how 2 addition operations can be time-multiplexed on a single pipelined hardware adder. The DSP program in Fig. 6.1(a) computes y(n) = a(n) + b(n) + c(n). In Fig. 6.1(b), the 2 addition operations shown in Fig. 6.1(a) are time-multiplexed on a single pipelined adder. The time-multiplexed hardware in Fig. 6.1(b) operates as follows. In cycle 0, the samples a(0) and b(0) are switched into the adder, and the sum (a(0) + b(0)) is stored in the delay element until cycle 1, when (a(0) + b(0)) is switched into the adder along with c(0). The ...

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