VLSI Digital Signal Processing Systems: Design and Implementation

17.7    CONCLUSIONS

This chapter has presented a comprehensive discussion on the design of low-power DSP systems. Different power optimization techniques such as path balancing, transistor sizing, transistor reordering, circuit styles, etc. are presented. These techniques can be used to achieve significant reduction in power consumption in digital systems. Finally, a tool for power estimation in digital systems is presented. This tool is fast due to its hierarchical nature and achieves accurate results. At algorithm level, power consumption can also be reduced by use of approximate processing where the filter length or the length of the DFT can be reduced dynamically for a marginal degradation of the system performance [43]. Furthermore, parameters such as wordlength can also be reduced by dynamic algorithm selection where the system SNR can be traded off for low power [44].