Verification Techniques for System-Level Design

Chapter 8. Simulation-Based Verification Techniques for System-Level Designs

Introduction

So far in this book, we have looked at various formal and semi-formal verification techniques and their applications to higher levels of design abstraction. In this chapter, we examine an old, well-known but extremely useful verification method: simulation. The basic concept of simulation is illustrated in Figure 8.1 and is essentially very straightforward. There is some specification of a design, and there is the implementation under verification that is supposed to adhere to the specification. For example, at the high level, the specification may be a text document written in natural language elaborating a standardized protocol. It may have some figures ...