T1: A Survival Guide

Slips: When Timing Goes Bad

T1 equipment employs a variety of techniques to compensate for variations in timing signals. Intermediate network equipment may buffer the 192-bit frames to ensure that frames are complete before forwarding them on to their destinations. CSU/DSUs are equipped with phase lock loop (PLL) circuitry to track with the more accurate clocks at the local exchange office. Occasionally, though, these measures are not enough, and timing problems occur.

Imperfect timing conditions may force network equipment to replicate or delete data in a process called a frame slip. Slips are divided into two categories. Controlled slips replicate or delete a complete 192-bit frame of data, but do not cause any problems with the T1 path. Uncontrolled slips, which are also called change of frame alignment (COFA) events, are much more severe because they disrupt the framing pattern. Controlled slips are the more benign of the two because the path remains available. Uncontrolled slips indicate more severe problems with the circuit.

Controlled slips always involve complete frames, and can be the result of either a buffer overflow or underflow. Both conditions are illustrated in Figure 5-12. In the overflow case, the second frame is lost in time unit 1 because the buffer overflows and replaces it with the third frame. Both the second frame and its framing bit are lost. Receivers use the disruption in the framing bit sequence to detect controlled slips. Controlled slips ...