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Microprocessor Theory and Applications with 68000/68020 and Pentium by M. Rafiquzzaman

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7

68000 HARDWARE AND INTERFACING

In this chapter we describe hardware aspects of the Motorola 68000. Topics include 68000 pins and signals, clock and reset circuits, timing diagrams, and memory and I/O interfacing techniques. Finally, the design of a 68000-based microcomputer is described along with memory and I/O maps.

7.1 68000 Pins And Signals

The 68000 is usually packaged in one of the following:

  • 64-pin dual in-line package (DIP)
  • 68-terminal chip carrier
  • 68-pin quad pack
  • 68-pin grid array (PGA)

Figure 7.1 shows the 68000 pin diagram for a DIP. For reliable operation, unused inputs should be connected to an appropriate signal level. Unused active LOW inputs should be connected to the Vcc. Unused active HIGH inputs should be connected to GROUND. Appendix C provides data sheets for the 68000 and support chips.

The 68000 is provided with two Vcc (+5 V) and two ground pins. Power is thus distributed to reduce noise problems at high frequencies. Also, to build a prototype to demonstrate that the paper design for the 68000-based microcomputer is correct, one must use either wire-wrap or solder for the actual construction. A breadboard should not be used, because at high frequencies (above 4 MHz), there will be noise problems due to stray capacitances. The 68000 consumes about 1.5 W of power.

D0–D15 are the 16 data bus pins. All transfers to and from memory and I/O devices are conducted over the 8-bit (LOW or HIGH) or 16-bit data bus depending on the size of the device. A1–A23 are ...

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