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Ethernet: The Definitive Guide, 2nd Edition by Joann Zimmerman, Charles E. Spurgeon

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Chapter 13. 100 Gigabit Ethernet

The development of 100 Gb/s Ethernet began with a Higher Speed Study Group “Call For Interest” meeting in July 2006. In response, an IEEE task force was formed to develop 100 Gb/s Ethernet specifications in the 802.3ba supplement. As described in the previous chapter, this effort was expanded to include 40 Gb/s Ethernet, and the combined 100 and 40 Gb/s 802.3ba supplement was completed and published in 2010.

The 40 and 100 Gb/s Ethernet systems were developed together and share the same basic architecture. This chapter describes the 100 Gb/s media types.

Architecture of 100 Gb/s Ethernet

The 100 Gb/s media system defines a physical layer (PHY) that is composed of a set of IEEE sublayers. Figure 13-1 shows the sublayers involved in the PHY. The standard defines a CGMII logical interface, using the Roman numeral C to indicate 100 Gb/s. This interface defines a 64-bit-wide path, over which frame data bits are sent to the PCS. The FEC and AN sublayers may or may not be used, depending on the media type involved.

100 Gb/s sublayers
Figure 13-1. 100 Gb/s sublayers

PCS Lanes

One important goal for the IEEE engineers working on the 802.3ba standard was to provide a system that could support both 40 and 100 billion bits per second. An equally vital goal was to implement those new Ethernet speeds with a technology that could be developed at a reasonable expense, and that could be expected ...

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