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Compact MOSFET Models for VLSI Design by A. B. Bhattacharyya

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7

Quantum Phenomena in MOS Transistors

7.1 Introduction

In modern VLSI chips the device density is increased by scaling down the device dimensions. An increase in device density increases the logic function implemented on the chip. The reduction in device dimensions introduces a number of undesirable second order effects on the IV characteristics of the device. As discussed in previous chapters the scaling theory proposes that these effects can be reduced by an increase in the substrate doping (> 5 × 1017 cm−3, and a decrease in the oxide thickness (< 50 Å). Such measures, however, increase the normal field in the gate oxide, as well as at the Si–SiO2 interface (F > 105 V cm−1) in silicon where the inversion layer is formed. The energy band diagram of a MOS structure under such a condition is shown in Figure 7.1, where the slope of the conduction band is proportional to the electric field component in the x-direction. When the electric field is high at the interface, the well in which the electrons are trapped is narrow, and its width is comparable to the De Broglie wavelength of the confined electrons. From quantum theory we know that in such a case the electron energy will be quantized in the conduction band, and the classical treatment does not hold good. The first two quantized energy levels are also shown in Figure 7.1.

Quantum confinement of the carriers leads to an increase in threshold voltage from that of the classical value. The gate capacitance also gets degraded in ...

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