VLSI Digital Signal Processing Systems: Design and Implementation

B.1    INTRODUCTION

Scheduling and allocation are two important tasks in hardware or software synthesis of DSP systems [1],[2]. They are both interrelated and dependent on each other and are among the most difficult problems of high-level synthesis. Scheduling involves assigning every node of the DFG to control time steps. Control time steps (or simply, time steps) are the fundamental sequencing units in synchronous systems and correspond to clock cycles. Resource allocation is the process of assigning operations to hardware with the goal of minimizing the amount of hardware required to implement the desired behavior. The hardware resources consist primarily of functional units, memory elements, multiplexers, and communication data paths.

DSP synthesis systems take a set of inputs, including a behavioral description of the algorithm, a set of resources and a set of constraints and goals, and generate a register-transfer level (RTL) architecture. The set of constraints and goals define the desired performance and characteristics of the final architecture. The most common constraints are area and performance constraints. Area constrained problems provide the designer with a set of resources (or more specifically a set of functional units), and the goal is to implement the application using those resources such that it has the highest performance. This is known as resource-constrained synthesis. The performance constrained problem is known as time-constrained synthesis, where the ...