VLSI Digital Signal Processing Systems: Design and Implementation

9.1    INTRODUCTION

This chapter presents applications of algorithmic strength reduction in parallel FIR filters, discrete cosine transforms (DCTs) and parallel rank-order filter. Strength reduction leads to a reduction in hardware complexity by exploiting substructure sharing. This transformation can lead to reduction in silicon area or power consumption in a VLSI implementation or iteration period in a programmable DSP implementation.

The FIR filter is one of the fundamental processing elements in any digital signal processing (DSP) system. FIR filters are used in DSP applications ranging from video and image processing to wireless communications. In some applications, such as video processing, the FIR filter circuit must be able to operate at high frequencies, while in other applications, such as cellular telephony, the FIR filter circuit must be a low-power circuit, capable of operating at moderate frequencies. Parallel, or block processing can be applied to digital FIR filters to either increase the effective throughput of the original filter or reduce the power consumption of the original filter. Traditionally, the application of parallel processing to an FIR filter involves the replication of the hardware units that exist in the original filter. If the area required by the original circuit is A, then the L-parallel circuit requires an area of L × A. In other words, the circuit area increases linearly with the block size. In many design situations, the hardware overhead incurred ...