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VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

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7.4    SELECTION OF SCHEDULING VECTOR

For any specified projection vector, processor space vector and scheduling vector, the systolic array can be designed using linear mapping technique. In this section, the method of selecting feasible scheduling vectors using scheduling inequalities is discussed. Based on the selected scheduling vector sT, the projection vector d and the processor space vector pT can be selected according to equations (7.3) and (7.2). Hence the desired systolic array can be obtained.

7.4.1    Selection of sT Based on Scheduling Inequalities

Consider the dependence relation XY,

image

where Ix and Iy are the indices of node X and node Y, respectively. The scheduling inequality for this dependence is defined as

image

where Tx is the time to compute node X and Sx, Sy are the scheduling times for nodes X, Y, respectively. The scheduling equations can be classified into 2 types:

  1. Linear scheduling, where

    image

  2. Affine scheduling, where

    image

Using the foregoing definition, we can rewrite the scheduling equation for affine scheduling as

Note that the scheduling equation for linear scheduling ...

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