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VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

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7.3    FIR SYSTOLIC ARRAYS

This section derives a family of systolic arrays for FIR digital filters using the linear mapping technique.

7.3.1    Design B1 (Broadcast Inputs, Move Results, Weights Stay)

The systolic design B1 is derived by selecting the projection vector, processor vector, and scheduling vector as follows:

image

Using these definitions, we can show that:

  • Any node with index IT = (i, j) is mapped to processor

    image

    Therefore, all nodes on a horizontal line are mapped to the same processor.

  • Any node with index IT = (i, j) is executed at time

    image

  • Since

    image

    then

    image

  • Edge mapping: The 3 fundamental edges corresponding to weight, input, and result can be mapped to corresponding edges in the systolic array according to Table 7.1.

Table 7.1    Edge Mapping Table for Design B1

image

The block diagram of B1 systolic array design is then constructed as shown in Fig. 7.3. The low-level implementation of ...

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