There are two main advantages of using pipelining and parallel processing:
It has already been shown that pipelining and parallel processing can increase the sample speed. Now consider use of these techniques for lowering the power consumption where sample speed does not need to be increased .
Before moving on, two formulas are reviewed: one for computing the propagation delay of CMOS circuits and the other for computing the power consumption. The propagation delay Tpd is associated with charging and discharging of the various gate and stray capacitances in the critical path. For CMOS circuits, the propagation delay can be written as:
where Ccharge denotes the capacitance to be charged/discharged in a single clock cycle, i.e., the capacitance along the critical path, V0 is the supply voltage and Vt is the threshold voltage. Parameter k is a function of technology parameters µ, , and Cox. The power consumption of a CMOS circuit can be estimated using the following equation,
where Ctotal denotes the total capacitance of the circuit, V0 is the supply voltage, and f is the clock frequency of the circuit. ...