## 3.4 PIPELINING AND PARALLEL PROCESSING FOR LOW POWER

There are two main advantages of using pipelining and parallel processing:

It has already been shown that pipelining and parallel processing can increase the sample speed. Now consider use of these techniques for lowering the power consumption where sample speed does not need to be increased [14].

Before moving on, two formulas are reviewed: one for computing the propagation delay of CMOS circuits and the other for computing the power consumption. The propagation delay *T*_{pd} is associated with charging and discharging of the various gate and stray capacitances in the critical path. For CMOS circuits, the propagation delay can be written as:

where *C*_{charge} denotes the capacitance to be charged/discharged in a single clock cycle, i.e., the capacitance along the critical path, *V*_{0} is the supply voltage and *V*_{t} is the threshold voltage. Parameter *k* is a function of technology parameters *µ*, , and *C*_{ox}. The power consumption of a CMOS circuit can be estimated using the following equation,

where *C*_{total} denotes the total capacitance of the circuit, *V*_{0} is the supply voltage, and *f* is the clock frequency of the circuit. ...