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VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

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17.4    POWER ANALYSIS

It is clear from Section 17.1 that essentially four factors determine the power dissipation in a digital CMOS circuit. However, reducing the clock frequency is generally not an option as all digital systems have certain minimum throughput requirements. The ramifications of scaling the supply voltage has already been discussed in the previous section. This section briefly analyzes the other two factors, namely switching activity and physical capacitance, describing their importance, as well as the interactions that make the design for low-power challenging.

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Fig. 17.4    Circuit delay as a function of supply voltage for varying threshold voltages.

17.4.1    Switching Activity

The switching activity of a circuit is the average number of 0 → 1 transitions that occur in 1 clock cycle at various output nodes in the circuit. It is difficult to estimate the switching activity for a general circuit because it is not only a function of the circuit inputs and the logic function the circuit implements but also a function of the temporal and spatial correlations among the circuit inputs. Furthermore, glitching or spurious transitions that occur at output nodes before they settle down also affect the switching activity.

The dependence of switching activity on the correlation among circuit inputs is illustrated with the help of a simple example. Consider an OR gate with ...

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