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VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi

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16.4    WAVE PIPELINING

It is clear from the previous section that clocking styles play a very important role in the performance of digital systems. Conventional methods involve the identification of the critical path (the path with the longest delay) for the determination of the clock period. Therefore, the designer spends most of the time in trying to minimize this clock period. In digital systems, typically there exist many paths having delays that are much smaller than the critical path. However, they are still clocked with the same clock period and as a result the logic gates along this path remain idle for a major portion of the clock period. This suggests that there is room for improvement in the clock speed where the noncritical paths remain idle. The concept of wave pipelining [4] is based on the fact that the clock speed can be increased if the idle time of the noncritical paths can be reduced.

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Fig. 16.17    Two-level distributed buffering scheme.

It is intuitive to observe from Fig. 16.1(b) that the inputs to the output register are all stable for a significant portion of the clock period, suggesting that the combinatorial block is not operating at its maximum rate. One may then ask the question, is it possible to apply a new set of operands to the input of the combinatorial block before the results of the current operand appear at its output. The answer is yes, and in ...

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