VLSI Digital Signal Processing Systems: Design and Implementation

16.12    PROBLEMS

1. Consider a typical sequential system shown in Fig. 16.59 which is designed using CLBs and latches (LATs). Let us assume that the input signal to the leftmost latch is [Vϕ₁] and that the latch is clocked using ϕ₁. Will this sequential circuit behave correctly? Explain. Also, what is the status of the signals at nodes 1–8, i.e., are they [Vϕ₁], [Vϕ₂], [Sϕ₁], or [Sϕ₂]? Explain which latches are clocked using ϕ₁ and which are clocked using ϕ₂.

   

   Fig. 16.59    A typical sequential system.

2. Consider the circuit shown in Fig. 16.60, where the input signal X is [Vϕ₁] and the input signal Y is [Sϕ₁]. The signal Z is used as the clock for the latch. Will this latch function correctly? If so, what is the main advantage of this circuit?

   

   Fig. 16.60    Circuit for Problem 2.

3. Draw the timing waveforms of ϕ, ϕ₁, and ϕ₂ for the circuit shown in Fig. 16.8 and verify the operation of the 2-phase clock generator.
4. Design a 9-transistor positive edge-triggered true single phase clocked flip-flop and explain its operation.
5. Let us assume that a bit-pipelined digital system is designed using a single-phase level sensitive clocking scheme with pulse width t_ϕ. Show that the clock skew δ for this clocking scheme is given by

   Explain the behavior of the circuit for both positive and negative ...