VLSI Digital Signal Processing Systems: Design and Implementation

16.11    CONCLUSIONS

This chapter has presented a comprehensive discussion of various pipelining styles. First, a detailed discussion of synchronous pipelining and various clocking styles was presented. Then, the problems of clock skew and clock distribution were addressed and methods to overcome them were presented. Two recent techniques, namely, wave pipelining and asynchronous pipelining were addressed in the remainder of the chapter. Wave pipelining was used to increase the number of pipeline stages without the use of physical registers. This was achieved by performing accurate timing analysis of the design both at the circuit level and at the system level. The absence of registers results in a simpler clock distribution. Moreover, a significantly higher throughput is achieved when compared to synchronous systems. An algorithm was also presented to systematically design wave-pipelined circuits.

Asynchronous pipelining is an alternate pipelining style where the use of a global clock signal is totally eliminated and communication is carried out using handshake signals. The chapter has presented different types of asynchronous circuits classified based upon the handshake signals. The design of 4-phase handshake circuits using signal transition graphs was also presented. Many examples illustrating the design of asynchronous computational units were also presented.