VLSI Digital Signal Processing Systems: Design and Implementation

15.1    INTRODUCTION

Strength reduction at the algorithm level can be used to reduce the number of additions and multiplications (see Chapter 9). This chapter covers numerical transformation techniques for reducing strength of DSP computations. These transformations rely upon subexpression elimination (also referred to as substructure sharing) to restructure the computation in such a manner that the performance, in terms of speed, power and area, of the computation can be improved. Section 15.2 addresses the basic concepts of subexpression elimination. Section 15.3 describes how subexpression elimination can be applied to the multiple constant multiplication problem. Multiple constant multiplication is then extended to specific computations such as linear transformation and polynomial evaluation. Section 15.4 shows how subexpression elimination can be applied to digital filters. Section 15.5 discusses the application of additive number splitting to linear transformations including a detailed discussion of row-based and column-based splitting. This section also discusses multiplicative number splitting and shows how the technique can be applied to linear transforms to either reduce the power or the area of an implementation. Strength reduction reduces the total capacitance and, therefore, reduces power consumption.