VLSI Digital Signal Processing Systems: Design and Implementation

13.1    INTRODUCTION

This chapter addresses the design of bit-level architectures for addition and multiplication frequently encountered in DSP algorithms. Three implementation styles, bit-parallel, bit-serial, and digit-serial are addressed. Bit-parallel systems process one whole word of the input sample each clock cycle and are ideal for high-speed applications. Bit-serial systems process 1 bit of the input sample every clock cycle. These systems can be synthesized using integer linear programming based scheduling approach (see Appendix F). Bit-serial systems are area-efficient and suitable for low-speed applications [1] – [3]. Bit-serial arithmetic is used for the implementation of data-flow algorithms of medium complexity and low to medium data rate, whereas bit-parallel operators may be used for the implementation of data-flow algorithms of low complexity and high data rate. Digit-serial systems [4],[5] process multiple number of bits (referred to as digit-size) every clock cycle and are best suited for applications requiring moderate sample rate, where area and power consumption are critical.

This chapter considers the design of bit-parallel and bit-serial multipliers, bit-serial digital filter design and implementations, and bit-level implementation schemes for vector-vector multiplications. The major emphasis is on architecture design based on design methodologies for mapping algorithms to arithmetic architectures at bit-level. Basic knowledge of computer arithmetic, such ...