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VLSI Digital Signal Processing Systems: Design and Implementation

Book Description

Digital audio, speech recognition, cable modems, radar, high-definition television-these are but a few of the modern computer and communications applications relying on digital signal processing (DSP) and the attendant application-specific integrated circuits (ASICs). As information-age industries constantly reinvent ASIC chips for lower power consumption and higher efficiency, there is a growing need for designers who are current and fluent in VLSI design methodologies for DSP.

Enter VLSI Digital Signal Processing Systems-a unique, comprehensive guide to performance optimization techniques in VLSI signal processing. Based on Keshab Parhi's highly respected and popular graduate-level courses, this volume is destined to become the standard text and reference in the field. This text integrates VLSI architecture theory and algorithms, addresses various architectures at the implementation level, and presents several approaches to analysis, estimation, and reduction of power consumption.

Throughout this book, Dr. Parhi explains how to design high-speed, low-area, and low-power VLSI systems for a broad range of DSP applications. He covers pipelining extensively as well as numerous other techniques, from parallel processing to scaling and roundoff noise computation. Readers are shown how to apply all techniques to improve implementations of several DSP algorithms, using both ASICs and off-the-shelf programmable digital signal processors.

The book features hundreds of graphs illustrating the various DSP algorithms, examples based on digital filters and transforms clarifying key concepts, and interesting end-of-chapter exercises that help match techniques with applications. In addition, the abundance of readily available techniques makes this an extremely useful resource for designers of DSP systems in wired, wireless, or multimedia communications. The material can be easily adopted in new courses on either VLSI digital signal processing architectures or high-performance VLSI system design.

An invaluable reference and practical guide to VLSI digital signal processing.

A tremendous source of optimization techniques indispensable in modern VLSI signal processing, VLSI Digital Signal Processing Systems promises to become the standard in the field. It offers a rich training ground for students of VLSI design for digital signal processing and provides immediate access to state-of-the-art, proven techniques for designers of DSP applications-in wired, wireless, or multimedia communications.

Topics include:

  • Transformations for high speed using pipelining, retiming, and parallel processing techniques

  • Power reduction transformations for supply voltage reduction as well as for strength or capacitance reduction

  • Area reduction using folding techniques

  • Strategies for arithmetic implementation

  • Synchronous, wave, and asynchronous pipelining

  • Design of programmable DSPs.

  • An Instructor's Manual presenting detailed solutions to all the problems in the book is available from the Wiley editorial department.

    Table of Contents

    1. Cover Page
    2. Halftitle Page
    3. Title Page
    4. Copyright
    5. Dedication
    6. Contents
    7. Preface
    8. 1 Introduction to Digital Signal Processing Systems
      1. 1.1 Introduction
      2. 1.2 Typical DSP Algorithms
      3. 1.3 DSP Application Demands and Scaled CMOS Technologies
      4. 1.4 Representations of DSP Algorithms
      5. 1.5 Book Outline
      6. References
    9. 2 Iteration Bound
      1. 2.1 Introduction
      2. 2.2 Data-Flow Graph Representations
      3. 2.3 Loop Bound and Iteration Bound
      4. 2.4 Algorithms for Computing Iteration Bound
      5. 2.5 Iteration Bound of Multirate Data-Flow Graphs
      6. 2.6 Conclusions
      7. 2.7 Problems
      8. References
    10. 3 Pipelining and Parallel Processing
      1. 3.1 Introduction
      2. 3.2 Pipelining of FIR Digital Filters
      3. 3.3 Parallel Processing
      4. 3.4 Pipelining and Parallel Processing for Low Power
      5. 3.5 Conclusions
      6. 3.6 Problems
      7. References
    11. 4 Retiming
      1. 4.1 Introduction
      2. 4.2 Definitions and Properties
      3. 4.3 Solving Systems of Inequalities
      4. 4.4 Retiming Techniques
      5. 4.5 Conclusions
      6. 4.6 Problems
      7. References
    12. 5 Unfolding
      1. 5.1 Introduction
      2. 5.2 An Algorithm for Unfolding
      3. 5.3 Properties of Unfolding
      4. 5.4 Critical Path, Unfolding, and Retiming
      5. 5.5 Applications of Unfolding
      6. 5.6 Conclusions
      7. 5.7 Problems
      8. References
    13. 6 Folding
      1. 6.1 Introduction
      2. 6.2 Folding Transformation
      3. 6.3 Register Minimization Techniques
      4. 6.4 Register Minimization in Folded Architectures
      5. 6.5 Folding of Multirate Systems
      6. 6.6 Conclusions
      7. 6.7 Problems
      8. References
    14. 7 Systolic Architecture Design
      1. 7.1 Introduction
      2. 7.2 Systolic Array Design Methodology
      3. 7.3 FIR Systolic Arrays
      4. 7.4 Selection of Scheduling Vector
      5. 7.5 Matrix-Matrix Multiplication and 2D Systolic Array Design
      6. 7.6 Systolic Design for Space Representations Containing Delays
      7. 7.7 Conclusions
      8. 7.8 Problems
      9. References
    15. 8 Fast Convolution
      1. 8.1 Introduction
      2. 8.2 Cook-Toom Algorithm
      3. 8.3 Winograd Algorithm
      4. 8.4 Iterated Convolution
      5. 8.5 Cyclic Convolution
      6. 8.6 Design of Fast Convolution Algorithm by Inspection
      7. 8.7 Conclusions
      8. 8.8 Problems
      9. References
    16. 9 Algorithmic Strength Reduction in Filters and Transforms
      1. 9.1 Introduction
      2. 9.2 Parallel FIR Filters
      3. 9.3 Discrete Cosine Transform and Inverse DCT
      4. 9.4 Parallel Architectures for Rank-Order Filters
      5. 9.5 Conclusions
      6. 9.6 Problems
      7. References
    17. 10 Pipelined and Parallel Recursive and Adaptive Filters
      1. 10.1 Introduction
      2. 10.2 Pipeline Interleaving in Digital Filters
      3. 10.3 Pipelining in lst-Order MR Digital Filters
      4. 10.4 Pipelining in Higher-Order IIR Digital Filters
      5. 10.5 Parallel Processing for IIR filters
      6. 10.6 Combined Pipelining and Parallel Processing for IIR Filters
      7. 10.7 Low-Power IIR Filter Design Using Pipelining and Parallel Processing
      8. 10.8 Pipelined Adaptive Digital Filters
      9. 10.9 Conclusions
      10. 10.10 Problems
      11. References
    18. 11 Scaling and Roundoff Noise
      1. 11.1 Introduction
      2. 11.2 Scaling and Roundoff Noise
      3. 11.3 State Variable Description of Digital Filters
      4. 11.4 Scaling and Roundoff Noise Computation
      5. 11.5 Roundoff Noise in Pipelined IIR Filters
      6. 11.6 Roundoff Noise Computation Using State Variable Description
      7. 11.7 Slow-Down, Retiming, and Pipelining
      8. 11.8 Conclusions
      9. 11.9 Problems
      10. References
    19. 12 Digital Lattice Filter Structures
      1. 12.1 Introduction
      2. 12.2 Schur Algorithm
      3. 12.3 Digital Basic Lattice Filters
      4. 12.4 Derivation of One-Multiplier Lattice Filter
      5. 12.5 Derivation of Normalized Lattice Filter
      6. 12.6 Derivation of Scaled-Normalized Lattice Filter
      7. 12.7 Roundoff Noise Calculation in Lattice Filters
      8. 12.8 Pipelining of Lattice IIR Digital Filters
      9. 12.9 Design Examples of Pipelined Lattice Filters
      10. 12.10 Low-Power CMOS Lattice IIR Filters
      11. 12.11 Conclusions
      12. 12.12 Problems
      13. References
    20. 13 Bit-Level Arithmetic Architectures
      1. 13.1 Introduction
      2. 13.2 Parallel Multipliers
      3. 13.3 Interleaved Floor-plan and Bit-Plane-Based Digital Filters
      4. 13.4 Bit-Serial Multipliers
      5. 13.5 Bit-Serial Filter Design and Implementation
      6. 13.6 Canonic Signed Digit Arithmetic
      7. 13.7 Distributed Arithmetic
      8. 13.8 Conclusions
      9. 13.9 Problems
      10. References
    21. 14 Redundant Arithmetic
      1. 14.1 Introduction
      2. 14.2 Redundant Number Representations
      3. 14.3 Carry-Free Radix-2 Addition and Subtraction
      4. 14.4 Hybrid Radix-4 Addition
      5. 14.5 Radix-2 Hybrid Redundant Multiplication Architectures
      6. 14.6 Data Format Conversion
      7. 14.7 Redundant to Nonredundant Converter
      8. 14.8 Conclusions
      9. 14.9 Problems
      10. References
    22. 15 Numerical Strength Reduction
      1. 15.1 Introduction
      2. 15.2 Subexpression Elimination
      3. 15.3 Multiple Constant Multiplication
      4. 15.4 Subexpression Sharing in Digital Filters
      5. 15.5 Additive and Multiplicative Number Splitting
      6. 15.6 Conclusions
      7. 15.7 Problems
      8. References
    23. 16 Synchronous, Wave, and Asynchronous Pipelines
      1. 16.1 Introduction
      2. 16.2 Synchronous Pipelining and Clocking Styles
      3. 16.3 Clock Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs
      4. 16.4 Wave Pipelining
      5. 16.5 Constraint Space Diagram and Degree of Wave Pipelining
      6. 16.6 Implementation of Wave-Pipelined Systems
      7. 16.7 Asynchronous Pipelining
      8. 16.8 Signal Transition Graphs
      9. 16.9 Use of STG to Design Interconnection Circuits
      10. 16.10 Implementation of Computational Units
      11. 16.11 Conclusions
      12. 16.12 Problems
      13. References
    24. 17 Low-Power Design
      1. 17.1 Introduction
      2. 17.2 Theoretical Background
      3. 17.3 Scaling Versus Power Consumption
      4. 17.4 Power Analysis
      5. 17.5 Power Reduction Techniques
      6. 17.6 Power Estimation Approaches
      7. 17.7 Conclusions
      8. 17.8 Problems
      9. References
    25. 18 Programmable Digital Signal Processors
      1. 18.1 Introduction
      2. 18.2 Evolution of Programmable Digital Signal Processors
      3. 18.3 Important Features of DSP Processors
      4. 18.4 DSP Processors for Mobile and Wireless Communications
      5. 18.5 Processors for Multimedia Signal Processing
      6. 18.6 Conclusions
      7. References
    26. Appendix A: Shortest Path Algorithms
      1. A.1 Introduction
      2. A.2 The Bellman-Ford Algorithm
      3. A.3 The Floyd-Warshall Algorithm
      4. A.4 Computational Complexities
      5. References
    27. Appendix B: Scheduling and Allocation Techniques
      1. B.1 Introduction
      2. B.2 Iterative/Constructive Scheduling Algorithms
      3. B.3 Transformational Scheduling Algorithms
      4. B.4 Integer Linear Programming Models
      5. References
    28. Appendix C: Euclidean GCD Algorithm
      1. C.1 Introduction
      2. C.2 Euclidean GCD Algorithm for Integers
      3. C.3 Euclidean GCD Algorithm for Polynomials
    29. Appendix D: Orthonormality of Schur Polynomials
      1. D.1 Orthogonality of Schur Polynomials
      2. D.2 Orthonormality of Schur Polynomials
    30. Appendix E: Fast Binary Adders and Multipliers
      1. E.1 Introduction
      2. E.2 Multiplexer-Based Fast Binary Adders
      3. E.3 Wallace Tree and Dadda Multiplier
      4. References
    31. Appendix F: Scheduling in Bit-Serial Systems
      1. F.1 Introduction
      2. F.2 Outline of the Scheduling Algorithm
      3. F.3 Minimum Cost Solution
      4. F.4 Scheduling of Edges with Delays
      5. References
    32. Appendix G: Coefficient Quantization in FIR Filters
      1. G.1 Introduction
      2. G.2 NUS Quantization Algorithm
      3. References
    33. Index
    34. Backcover