Book description
This book discusses practical implementation architectures for modern error-correcting codes, providing details for every functional block as well as the overall decoder architecture. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. Many examples and case studies are included. More importantly, the advantages and drawbacks of different implementation approaches and architectures are compared. Thus, this book makes an ideal reference for system and hardware designers and graduate-level courses on VLSI design and error-correcting coding.
Table of contents
- Cover Page
- Half title
- Title Page
- Copyright page
- Dedication
- Contents
- Preface
- List of Figures
- List of Tables
- 1 Finite field arithmetic
- 2 VLSI architecture design fundamentals
- 3 Root computations for polynomials over finite fields
- 4 Reed-Solomon encoder & hard-decision and erasure decoder architectures
-
5. Algebraic soft-decision Reed-Solomon decoder architectures
- 5.1 Algebraic soft-decision decoding algorithms
- 5.2 Re-encoded algebraic soft-decision decoder
- 5.3 Re-encoding algorithms and architectures
- 5.4 Interpolation algorithms and architectures
- 5.5 Factorization algorithm and architectures
-
6 Interpolation-based Chase and generalized minimum distance decoders
- 6.1 Interpolation-based Chase decoder
- 6.2 Generalized minimum distance decoder
- 7 BCH encoder & decoder architectures
- 8 Binary LDPC codes & decoder architectures
-
9 Non-binary LDPC decoder architectures
- 9.1 Non-binary LDPC codes and decoding algorithms
-
9.2 Min-max decoder architectures
- 9.2.1 Forward-backward Min-max check node processing
- 9.2.2 Trellis-based path-construction Min-max check node processing
- 9.2.3 Simplified Min-max check node processing
- 9.2.4 Syndrome-based Min-max check node processing
- 9.2.5 Basis-construction Min-max check node processing
- 9.2.6 Variable node unit architectures
- 9.2.7 Overall NB-LDPC decoder architectures
- 9.3 Extended Min-sum decoder architectures
- 9.4 Iterative majority-logic decoder architectures
- Bibliography
- Index
Product information
- Title: VLSI Architectures for Modern Error-Correcting Codes
- Author(s):
- Release date: December 2017
- Publisher(s): CRC Press
- ISBN: 9781351831222
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