VHDL

Lesson Plan

This lesson plan is for undergraduate/postgraduate engineering students (ECE/EE/CSE), based on the assumption that there will be three lectures per week and at least 12 weeks in a semester of 4 months

Lecture No.	Topics
L1	CHAPTER 1INTRODUCTION   Design Flow   EDA Tools for DesignROLE OF HDL’s   Introduction to HDLs   Different HDLs
L2	CHAPTER 2HISTORY OF VHDLCOMPARISON BETWEEN VHDL AND VERILOGFEATURES OF VHDL
L3	BASIC TERMINOLOGIES OF VHDLLEVELS OF HARDWARE ABSTRACTION   Overview   Entity Declaration   Architecture Body   Styles of Modelling   Simple Example of VHDL
L4	DELAY MODELS IN VHDL   Transport Delay   Inertial Delay   Delta Delay
L5	CHAPTER 3INTRODUCTION   IdentifiersDATA OBJECTS   Signal   Variable   Constant ...