VHDL

3

Basic Language Elements

CHAPTER OBJECTIVES

• To familiarize with the basic elements of VHDL
• Understand the rules governing user-defined names
• Learn data types and their use in VHDL
• Define and use user-defined data types as required
• Understand basic operators in VHDL

3.1 INTRODUCTION

This chapter introduces the basic language elements in VHDL. Before learning the circuit design of the circuits using VHDL, it is important to get familiar with the basic syntax, keywords and the allowed data types of VHDL. First of all, when writing a hardware model in VHDL, it is important to annotate the code with comments. The comment in VHDL is identified by two consecutive dashes (--) followed by a comment text.

FOR EXAMPLE:

-- this is a comment

The ...