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VHDL

Book Description

VHDL: Basics to Programming is ideal for undergraduate and graduate students of Electronics Engineering, Computer Engineering and Information Technology. VHDL: Basics to Programming is a methodological guide to VHDL and its applications. It

Table of Contents

  1. Cover
  2. Title Page
  3. Contents
  4. About the Author
  5. Preface
  6. Lesson Plan
  7. Chapter 1. Digital Design Flow
    1. 1.1 Introduction
      1. 1.1.1 Design Flow
      2. 1.1.2 EDA Tools for Design
    2. 1.2 Role of Hdl
      1. 1.2.1 Introduction to HDLs
      2. 1.2.2 Evolution of HDLs
      3. 1.2.3 Different HDLs
    3. Summary
    4. Questions
  8. Chapter 2. Introduction to VHDL
    1. 2.1 History of VHDL
    2. 2.2 Comparison Between VHDL and Verilog
    3. 2.3 Features of VHDL
    4. 2.4 Basic Terminologies of VHDL
    5. 2.5 Levels of Hardware Abstraction
      1. 2.5.1 Overview
      2. 2.5.2 Entity Declaration
      3. 2.5.3 Architecture Body
      4. 2.5.4 Styles of Modelling
      5. 2.5.5 A Simple Coding Example in VHDL
    6. 2.6 Delay Models in VHDL
      1. 2.6.1 Inertial Delay Model
      2. 2.6.2 Transport Delay Model
      3. 2.6.3 Delta Delay Model
      4. 2.6.4 Differences Between Inertial Delay and Transport Delay
    7. Summary
    8. Questions
  9. Chapter 3. Basic Language Elements
    1. 3.1 Introduction
      1. 3.1.1 Identifiers
    2. 3.2 Data Objects
      1. 3.2.1 Constant
      2. 3.2.2 Variable
      3. 3.2.3 Signals
    3. 3.3 Data Types
      1. 3.3.1 Predefined Types
      2. 3.3.2 Scalar Type
      3. 3.3.3 Composite Type
      4. 3.3.4 Access Type
      5. 3.3.5 File Type
    4. 3.4 Operators
      1. 3.4.1 Arithmetic Operators
      2. 3.4.2 Logical Operators
      3. 3.4.3 Relational Operators
      4. 3.4.4 Shift-and-Rotate Operators
      5. 3.4.5 Miscellaneous Operators
    5. Summary
    6. Questions
  10. Chapter 4. Behavioural Modelling
    1. 4.1 Introduction
    2. 4.2 Sequential Vs Concurrent Statements
    3. 4.3 Process Statement
      1. 4.3.1 Sensitivity List
    4. 4.4 Variables
      1. 4.4.1 Differences Between a Signal and a Variable
    5. 4.5 Sequential Statements
      1. 4.5.1 If Statement
      2. 4.5.2 Case Statement
      3. 4.5.3 Loop Statement
      4. 4.5.4 Wait Statement
      5. 4.5.5 Assert Statement
      6. 4.5.6 Exit Statement
      7. 4.5.7 Next Statement
      8. 4.5.8 Null Statement
    6. 4.6 Postponed Processes
    7. 4.7 Passive Processes
    8. Summary
    9. Questions
  11. Chapter 5. Dataflow Modelling
    1. 5.1 Introduction
    2. 5.2 Conditional Assignment Statements
      1. 5.2.1 When-Else
      2. 5.2.2 With-When-Select
    3. 5.3 Block Statement
    4. 5.4 Concurrent Assert Statement
    5. 5.5 Concept of Delay in Concurrent Logic
    6. Summary
    7. Questions
  12. Chapter 6. Structural Modelling
    1. 6.1 Introduction
    2. 6.2 Component Declaration
    3. 6.3 Component Instantiation
    4. 6.4 Generics
      1. 6.4.1 Introduction
      2. 6.4.2 Generic Map
      3. 6.4.3 Generics with Behavioural Modelling
    5. Summary
    6. Questions
  13. Chapter 7. Subprograms and Overloading
    1. 7.1 Introduction
    2. 7.2 Functions
    3. 7.3 Using Functions
      1. 7.3.1 Function in the Main Code
      2. 7.3.2 Function Inside Package
      3. 7.3.3 Scope of Function
    4. 7.4 Types of Function
    5. 7.5 Procedures
    6. 7.6 Using Procedures
    7. 7.7 Differences Between Functions and Procedures
    8. 7.8 Overloading
      1. 7.8.1 Subprogram Overloading
      2. 7.8.2 Overloading Operators
    9. Summary
    10. Questions
  14. Chapter 8. Configurations and Packages
    1. 8.1 Introduction to Configurations
      1. 8.1.1 Need for Configurations
    2. 8.2 Writing Configuration
      1. 8.2.1 Entity–Architecture Pair Configuration
      2. 8.2.2 Component–Entity Binding Configuration Specification
    3. 8.3 Introduction to Packages
    4. 8.4 Writing a Package
    5. 8.5 Using Package
    6. Summary
    7. Questions
  15. Chapter 9. Advanced Programming Concepts
    1. 9.1 Multiple Drivers
    2. 9.2 Attributes
      1. 9.2.1 Value Attributes
      2. 9.2.2 Function Attributes
      3. 9.2.3 Type Attributes
      4. 9.2.4 Range Attributes
    3. 9.3 Libraries
    4. 9.4 Alias
    5. 9.5 Signatures
    6. 9.6 Qualified Expressions
    7. 9.7 Generate Statement
    8. 9.8 Null Transactions
    9. Summary
    10. Questions
  16. Chapter 10. Testbenches
    1. 10.1 Introduction
      1. 10.1.1 Advantages of Using Testbenches
    2. 10.2 Writing a Testbench
    3. 10.3 Waveform Generation
    4. Summary
    5. Questions
  17. Chapter 11. Circuit Synthesis
    1. 11.1 Introduction
    2. 11.2 Differences Between Simulation and Synthesis
    3. 11.3 Synthesis Flow
    4. 11.4 Synthesizing Data Types
    5. 11.5 Synthesis of Combinational Logic
    6. 11.6 Synthesizing Sequential Logic
    7. 11.7 Modelling Finite State Machines
    8. Summary
    9. Questions
  18. Chapter 12. Embedded Design Using VHDL
    1. 12.1 Introduction
    2. 12.2 Architecture of Embedded System
    3. 12.3 Design Flow for Embedded System Design
    4. 12.4 Issues in Embedded System Design
      1. 12.4.1 Design Optimizations
    5. 12.5 Limitations of VHDL in the Embedded System Design
    6. Summary
    7. Questions
  19. Chapter 13. Microcomputer Design
    1. 13.1 Introduction
      1. 13.1.1 Basic Components of a Microcomputer
    2. 13.2 Implementation of Microcomputer using VHDL
    3. Summary
    4. Questions
  20. Chapter 14. Programmable Logic Devices
    1. 14.1 Introduction
    2. 14.2 Types of Plds
      1. 14.2.1 Plas (Programmable Logic Arrays)
      2. 14.2.2 Pals
      3. 14.2.3 Registered PALs
      4. 14.2.4 Gals (Generic Array Logic)
      5. 14.2.5 Macrocell Structure
    3. 14.3 Advantages of Using Plds
    4. 14.4 Cplds And Fpgas
      1. 14.4.1 CPLDs
      2. 14.4.2 Fpgas (Field Programmable Gate Array)
      3. 14.4.3 Differences Between Fpgas and Cplds
      4. 14.4.4 Implementation Using Fpgas and Cplds
    5. Summary
    6. Questions
  21. Chapter 15. Case Study—Genetic Algorithm Processor
    1. 15.1 Introduction to Genetic Algorithms
    2. 15.2 Hardware Ga
    3. 15.3 Architecture of Gap
    4. 15.4 Implementing the Modules for Gap
      1. 15.4.1 Processing Unit
    5. 15.5 Future Scope
  22. Additional Case Studies
  23. Appendix A. Xilinx 9.1 Tutorial
  24. Appendix B. Synthesizable Constructs of VHDL-93 and VHDL-2008
  25. Appendix C. VHDL-2008: New Features
  26. Appendix D. VHDL-AMS
  27. Appendix E. Unsolved Design Problems
  28. Acknowledgements
  29. Copyright