Index
‘−’ don’t care value of std_ulogic
− sign operator
− subtract operator
& concatenation operator
* multiplication operator
** exponentiation operator
/ division operator
/= not-equal operator
:= variable assignment
| bar symbol
aggregates
case statements
selected signal assignment
+ add operator
+ sign operator
< less-than operator
<= less-than-or-equal operator
<= signal assignment
<> box symbol
= equal operator
=> finger
array aggregates
case statement
generic map
port map
record aggregates
> greater-than operator
>= greater-than-or-equal operator
‘0’ low value of std_ulogic
0.0 (zero) floating-point value
‘1’ high value of std_ulogic
1076, IEEE standard. See Standards
1164, IEEE standard. See Standards
2's-complement notation
32-bit integer limit
754, IEEE standard. See Standards
Absolute value (abs) operator
Access types
line type in textio
Accidental feedback
Accumulator, case study
Active signal
Add (+) operator
Add_carry procedure
Adding operators
Address generator, case study
After clause
Aggregates
array targets
array types
as record targets
constant values
look-up table
named association
of aggregates
others clause
positional association
record types
All selection
component binding
use clause
Allocation and Scheduling
Analog and Mixed-Signal Working Group
Analysis. See Compilation
Analysis and Standardization Group, VHDL
And operator
Anonymous array types
Arbitrary-precision
fixed-point types
floating-point types
numeric types
Architecture
declaration part
generic ...
