List of Figures
Figure 1.1 The VHDL-based hardware design cycle
Figure 2.1 Cross-product calculator – data-flow diagram
Figure 2.2 Adder – balanced tree
Figure 2.3 Adder – skewed tree
Figure 2.4 Cross-product calculator – datapath
Figure 2.5 Cross-product calculator – controller
Figure 3.1 Adder tree circuit
Figure 3.2 Hardware mapping of conditional signal assignment
Figure 3.3 Multi-way conditional signal assignment
Figure 3.4 Redundant branch in conditional signal assignment
Figure 3.5 Parity generator interface
Figure 4.1 Using boolean as a comparison result
Figure 4.2 Intermediate value precisions
Figure 4.3 Multi-way selected signal assignment
Figure 5.1 Basic and operator
Figure 5.2 Selecting and operator
Figure 5.3 Reducing and operator
Figure 5.4 Four-bit equality
Figure 5.5 Four-bit less-than circuit
Figure 5.6 Array equality for arrays of equal length
Figure 5.7 Array less-than operator
Figure 5.8 Shift-left logical (sll) by 4 bits
Figure 5.9 Shift-left arithmetic (sla) by 4 bits
Figure 5.10 Rotate-left (rol) by 1 bit
Figure 5.11 Abs operator
Figure 5.12 Mapping of modulo-4 operator
Figure 5.13 Unsigned and signed modulo-4
Figure 5.14 Mapping of remainder operator
Figure 6.1 Signed resize to a larger size
Figure 6.2 Unsigned resize to a larger size
Figure 6.3 Signed resize to a smaller size
Figure 6.4 Unsigned resize to a smaller size
Figure 6.5 Fixed-point storage format
Figure 6.6 Floating-point storage format
Figure 8.1 Multiplexer interpretation of if statement ...
