Appendix B
Syntax Reference
This section gives the syntax of the main synthesis structures introduced throughout the book. It only covers the synthesis subset, not the whole language, and it excludes structures used for test benches.
B.1 Keywords
The following are the keywords in VHDL. Since these are reserved words, they cannot be used as names of signals, variables, functions or design units. In addition to this set of keywords, you should not use the name work as the name of a library.
abs access after alias all and architecture array assert assume
assume_guarantee attribute
begin block body buffer bus
case component configuration constant context cover
default disconnect downto
else elsif end entity exit
fairness file for force function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod
nand new next nor not null
of on open or others out
package parameter port postponed procedure process property pro
tected pure
range record register reject release rem report restrict
restrict_guarantee return rol ror
select sequence severity shared signal sla sll sra srl strong
subtype then to transport type
unaffected units until use
variable vmode vprop vunit
wait when while with
xnor xor
B.2 Design Units
All design units can be preceded by context items:
context ::= { use_clause | library_clause | context_clause }
use_clause ::= use selected_name { , selected_name } ;
library_clause ::= library identifier { , identifier } ;
context_clause ...
