Chapter 2. Other Major Features
The enhancement of generics that we described in Chapter 1 is one of several major new features in VHDL. In this chapter, we highlight the other major features that bring significant new power to the language.
External Names
One of the characteristics of VHDL is that it allows a verification testbench to be written in the same language as the design to be verified. However, some aspects of earlier versions of VHDL make it hard to verify designs. In particular, the scope and visibility rules are intended to help us manage name spaces in complex designs by enforcing abstraction of interfaces and hiding of internal information. While they are good for a design in isolation, they can prevent a testbench from accessing ...
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