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Vertical 3D Memory Technologies

Book Description

The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via connections now and remote links later.

Key features:

  • Presents a review of the status and trends in 3-dimensional vertical memory chip technologies.

  • Extensively reviews advanced vertical memory chip technology and development

  • Explores technology process routes and 3D chip integration in a single reference

  • Table of Contents

    1. Cover
    2. Title Page
    3. Copyright
    4. Acknowledgments
    5. Chapter 1: Basic Memory Device Trends Toward the Vertical
      1. 1.1 Overview of 3D Vertical Memory Book
      2. 1.2 Moore's Law and Scaling
      3. 1.3 Early RAM 3D Memory
      4. 1.4 Early Nonvolatile Memories Evolve to 3D
      5. 1.5 3D Cross-Point Arrays with Resistance RAM
      6. 1.6 STT-MTJ Resistance Switches in 3D
      7. 1.7 The Role of Emerging Memories in 3D Vertical Memories
      8. References
    6. Chapter 2: 3D Memory Using Double-Gate, Folded, TFT, and Stacked Crystal Silicon
      1. 2.1 Introduction
      2. 2.2 FinFET—Early Vertical Memories
      3. 2.3 Double-Gate and Tri-Gate Flash
      4. 2.4 Thin-Film Transistor (TFT) Nonvolatile Memory with Polysilicon Channels
      5. 2.5 Double-Gate Vertical Channel Flash Memory with Engineered Tunnel Layer
      6. 2.6 Stacked Gated Twin-Bit (SGTB) CT Flash
      7. 2.7 Crystalline Silicon and Epitaxial Stacked Layers
      8. References
    7. Chapter 3: Gate-All-Around (GAA) Nanowire for Vertical Memory
      1. 3.1 Overview of GAA Nanowire Memories
      2. 3.2 Single-Crystal Silicon GAA Nanowire CT Memories
      3. 3.3 Polysilicon GAA Nanowire CT Memories
      4. 3.4 Junctionless GAA CT Nanowire Memories
      5. 3.5 3D Stacked Horizontal Nanowire Single-Crystal Silicon Memory
      6. 3.6 Vertical Single-Crystal GAA CT Nanowire Flash Technology
      7. 3.7 Vertical Channel Polysilicon GAA CT Memory
      8. 3.8 Graphene Channel Nonvolatile Memory with Al2O3–HfOx–Al2O3 Storage Layer
      9. 3.9 Cost Analysis for 3D GAA NAND Flash Considering Channel Slope
      10. References
    8. Chapter 4: Vertical NAND Flash
      1. 4.1 Overview of 3D Vertical NAND Trends
      2. 4.2 Vertical Channel (Pipe) CT NAND Flash Technology
      3. 4.3 3D FG NAND Flash Cell Arrays
      4. 4.4 3D Stacked NAND Flash with Lateral BL Layers and Vertical Gate
      5. References
    9. Chapter 5: 3D Cross-Point Array Memory
      1. 5.1 Overview of Cross-Point Array Memory
      2. 5.2 A Brief Background of Cross-Point Array Memories
      3. 5.3 Low-Resistance Interconnects for Cross-Point Arrays
      4. 5.4 Cross-Point Array Memories Without Cell Selectors
      5. 5.5 Examples of Selectorless Cross-Point Arrays
      6. 5.6 Unipolar Resistance RAMs with Diode Selectors in Cross-Point Arrays
      7. 5.7 Unipolar PCM with Two-Terminal Diodes for Cross-Point Array
      8. 5.8 Bipolar Resistance RAMS With Selector Devices in Cross-Point Arrays
      9. 5.9 Complementary Switching Devices and Arrays
      10. 5.10 Toward Manufacturable ReRAM Cells and Cross-point Arrays
      11. 5.11 STT Magnetic Tunnel Junction Resistance Switches in Cross-Point Array Architecture
      12. References
    10. Chapter 6: 3D Stacking of RAM–Processor Chips Using TSV
      1. 6.1 Overview of 3D Stacking of RAM–Processor Chips with TSV
      2. 6.2 Architecture and Design of TSV RAM–Processor Chips
      3. 6.3 Process and Fabrication of Vertical TSV for Memory and Logic
      4. 6.4 Process and Fabrication Issues of TSV 3D Stacking Technology
      5. 6.5 Fabrication of TSVs
      6. 6.6 Energy Efficiency Considerations of 3D Stacked Memory–Logic Chip Systems
      7. 6.7 Thermal Characterization Analysis and Modeling of RAM–Logic Stacks
      8. 6.8 Testing of 3D Stacked TSV System Chips
      9. 6.9 Reliability Considerations with 3D TSV RAM–Processor Chips
      10. 6.10 Reconfiguring Stacked TSV Memory Architectures for Improved Performance
      11. 6.11 Stacking Memories Using Noncontact Connections with Inductive Coupling
      12. References
    11. Index
    12. End User License Agreement