Verilog Coding for Logic Synthesis

Verilog Coding for Logic Synthesis

Released April 2003
Publisher(s): Wiley-Interscience
ISBN: 9780471429760

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Book description

Provides a practical approach to Verilog design and problem solving.

  • Bulk of the book deals with practical design problems that design engineers solve on a daily basis.

  • Includes over 90 design examples.

  • There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.

  • Book is suitable for use as a textbook in EE departments that have VLSI courses

Table of contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Dedication
  5. Contents
  6. Table of Figures
  7. Table Of Examples
  8. List Of Tables
  9. Preface
  10. Acknowledgments
  11. Trademarks
  12. CHAPTER ONE: Introduction
  13. CHAPTER TWO: ASIC Design Flow
    1. 2.1 SPECIFICATION
    2. 2.2 RTL CODING
    3. 2.3 TEST BENCH AND SIMULATION
    4. 2.4 SYNTHESIS
    5. 2.5 PRE-LAYOUT TIMING ANALYSIS
    6. 2.6 APR
    7. 2.7 BACK ANNOTATION
    8. 2.8 POST-LAYOUT TIMING ANALYSIS
    9. 2.9 LOGIC VERIFICATION
  14. CHAPTER THREE: Verilog Coding
    1. 3.1 INTRODUCTION TO BASIC VERILOG CONCEPTS
    2. 3.2 VERILOG GATE-LEVEL PRIMITIVES
    3. 3.3 USER-DEFINED PRIMITIVES
    4. 3.4 CONCURRENT AND SEQUENTIAL STATEMENTS
  15. CHAPTER FOUR: Coding Style: Best-Known Method for Synthesis
    1. 4.1 NAMING CONVENTION
    2. 4.2 DESIGN PARTITIONING
    3. 4.3 CLOCK
    4. 4.4 RESET
    5. 4.5 TIMING LOOP
    6. 4.6 BLOCKING AND NONBLOCKING STATEMENTS
    7. 4.7 SENSITIVITY LIST
    8. 4.8 VERILOG OPERATORS
    9. 4.9 LATCH INFERENCE
    10. 4.10 MEMORY ARRAY
    11. 4.11 STATE MACHINE DESIGN
  16. CHAPTER FIVE: Design Example of Programmable Timer
    1. 5.1 PROGRAMMABLE TIMER DESIGN SPECIFICATION
    2. 5.2 MICROARCHITECTURE DEFINITION FOR PROGRAMMABLE TIMER
    3. 5.3 FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE TIMER
    4. 5.4 VERILOG CODE FOR PROGRAMMABLE TIMER
    5. 5.5 SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE TIMER
  17. CHAPTER SIX: Design Example of Programmable Logic Block for Peripheral Interface
    1. 6.1 PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE DESIGN SPECIFICATION
    2. 6.2 MODE OF OPERATION FOR PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE
    3. 6.3 MICRO-ARCHITECTURE DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE
    4. 6.4 FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE
    5. 6.5 SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE PERIPHERAL INTERFACE
    6. 6.6 SIMULATION FOR PROGRAMMABLE PERIPHERAL INTERFACE DESIGN
  18. Appendix
    1. APPENDIX A.1 TWO-BIT BY TWO-BIT ADDER
    2. APPENDIX A.2 TWO-BIT BY TWO-BIT SUBTRACTOR
    3. APPENDIX A.3 FOUR-BIT BY FOUR-BIT MULTIPLIER
  19. Glossary
  20. Bibliography
  21. Index

Product information

  • Title: Verilog Coding for Logic Synthesis
  • Author(s):
  • Release date: April 2003
  • Publisher(s): Wiley-Interscience
  • ISBN: 9780471429760