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Top-Down Digital VLSI Design

Book Description

Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin’s approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices.

Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more.



  • Demonstrates a top-down approach to digital VLSI design.
  • Provides a systematic overview of architecture optimization techniques.
  • Features a chapter on field-programmable logic devices, their technologies and architectures.
  • Includes checklists, hints, and warnings for various design situations.
  • Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Preface
    1. Why this book?
    2. Highlights
    3. Notes to instructors
  6. Acknowledgments
  7. Chapter 1: Introduction to Microelectronics
    1. Abstract
    2. 1.1 Economic impact
    3. 1.2 Microelectronics viewed from different perspectives
    4. 1.3 The VLSI design flow
    5. 1.4 Problems
    6. 1.5 Appendix I: a brief glossary of logic families
    7. 1.6 Appendix II: an illustrated glossary of circuit-related terms
  8. Chapter 2: Field-Programmable Logic
    1. Abstract
    2. 2.1 General idea
    3. 2.2 Configuration technologies
    4. 2.3 Organization of hardware resources
    5. 2.4 Commercial aspects
    6. 2.5 Extensions of the basic idea
    7. 2.6 The FPL design flow
    8. 2.7 Conclusions
  9. Chapter 3: From Algorithms to Architectures
    1. Abstract
    2. 3.1 The goals of architecture design
    3. 3.2 The architectural solution space
    4. 3.3 Dedicated vlsi architectures and how to design them
    5. 3.4 Equivalence transforms for combinational computations
    6. 3.5 Options for temporary storage of data
    7. 3.6 Equivalence transforms for non-recursive computations
    8. 3.7 Equivalence transforms for recursive computations
    9. 3.8 Generalizations of the transform approach
    10. 3.9 Conclusions
    11. 3.10 Problems
    12. 3.11 Appendix I: A brief glossary of algebraic structures
    13. 3.12 Appendix II: Area and delay figures of VLSI subfunctions
  10. Chapter 4: Circuit Modeling with Hardware Description Languages
    1. Abstract
    2. 4.1 Motivation and background
    3. 4.2 Key concepts and constructs of VHDL
    4. 4.2.3 A discrete replacement for electrical signals
    5. 4.2.4 An event-driven scheme of execution
    6. 4.2.5 Facilities for model parametrization
    7. 4.2.6 Concepts borrowed from programming languages
    8. 4.3 Key concepts and constructs of systemverilog
    9. 4.3.6 Concepts borrowed from programming languages
    10. 4.4 Automatic circuit synthesis from hdl models
    11. 4.5 Conclusions
    12. 4.6 Problems
    13. 4.7 Appendix I: VHDL and systemverilog side by side
    14. 4.8 Appendix II: VHDL extensions and standards
  11. Chapter 5: Functional Verification
    1. Abstract
    2. 5.1 Goals of design verification
    3. 5.2 How to establish valid functional specifications
    4. 5.3 Preparing effective simulation and test vectors
    5. 5.4 Consistency and efficiency considerations
    6. 5.5 Testbench coding and hdl simulation
    7. 5.6 Conclusions
    8. 5.7 Problems
    9. 5.8 Appendix I: Formal approaches to functional verification
    10. 5.9 Appendix II: Deriving a coherent schedule for simulation and test
  12. Chapter 6: The Case For Synchronous Design
    1. Abstract
    2. 6.1 Introduction
    3. 6.2 The grand alternatives for regulating state changes
    4. 6.3 Why a rigorous approach to clocking is essential in VLSI
    5. 6.4 The dos and donts of synchronous circuit design
    6. 6.5 Conclusions
    7. 6.6 Problems
    8. 6.7 Appendix: on identifying signals
  13. Chapter 7: Clocking of Synchronous Circuits
    1. Abstract
    2. 7.1 What is the difficulty with clock distribution?
    3. 7.2 How much skew and jitter does a circuit tolerate?
    4. 7.3 How to keep clock skew within tight bounds
    5. 7.4 How to achieve friendly input/output timing
    6. 7.5 How to implement clock gating properly
    7. 7.6 Summary
    8. 7.7 Problems
  14. Chapter 8: Acquisition of Asynchronous Data
    1. Abstract
    2. 8.1 Motivation
    3. 8.2 Data consistency in vectored acquisition
    4. 8.3 Data consistency in scalar acquisition
    5. 8.4 Marginal triggering and metastability
    6. 8.5 Summary
    7. 8.6 Problems
  15. Appendix A: Elementary Digital Electronics
    1. A.1 Introduction
    2. A.2 Theoretical background of combinational logic
    3. A.3 Circuit alternatives for implementing combinational logic
    4. A.4 Bistables and other memory circuits
    5. A.5 Transient behavior of logic circuits
    6. A.6 Timing quantities
    7. A.7 Basic microprocessor input/output transfer protocols
    8. A.8 Summary
  16. Appendix B: Finite State Machines
    1. B.1 Abstract automata
    2. B.2 Practical aspects and implementation issues
    3. B.3 Summary
  17. Appendix C: Symbols and Constants
    1. C.1 Abbreviations
    2. C.2 Mathematical symbols
    3. C.3 Physical and material constants
  18. Bibliography
  19. Index