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Three-dimensional Integrated Circuit Design

Book Description

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.

* Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

Table of Contents

  1. Cover
  2. Title
  3. Brief Table of Contents
  4. Table of Contents
  5. Copyright
  6. Dedication
  7. Preface
  8. Chapter 1. Introduction
    1. 1.1. From the Integrated Circuit to the Computer
    2. 1.2. Interconnects, an Old Friend
    3. 1.3. Three-Dimensional or Vertical Integration
    4. 1.4. Book Organization
  9. Chapter 2. Manufacturing of 3-D Packaged Systems
    1. 2.1. Three-Dimensional Integration
    2. 2.2. System-on-Package
    3. 2.3. Technologies for System-in-Package
    4. 2.4. Cost Issues for 3-D Integrated Systems
    5. 2.5. Summary
  10. Chapter 3. 3-D Integrated Circuit Fabrication Technologies
    1. 3.1. Monolithic 3-D ICs
    2. 3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias
    3. 3.3. Contactless 3-D ICs
    4. 3.4. Vertical Interconnects for 3-D ICs
    5. 3.5. Summary
  11. Chapter 4. Interconnect Prediction Models
    1. 4.1. Interconnect Prediction Models for 2-D Circuits
    2. 4.2. Interconnect Prediction Models for 3-D ICs
    3. 4.3. Projections for 3-D ICs
    4. 4.4. Summary
  12. Chapter 5. Physical Design Techniques for 3-D ICs
    1. 5.1. Floorplanning Techniques
    2. 5.2. Placement Techniques
    3. 5.3. Routing Techniques
    4. 5.4. Layout Tools
    5. 5.5. Summary
  13. Chapter 6. Thermal Management Techniques
    1. 6.1. Thermal Analysis of 3-D ICs
    2. 6.2. Thermal Management Techniques without Thermal Vias
    3. 6.3. Thermal Management Techniques Employing Thermal Vias
    4. 6.4. Summary
  14. Chapter 7. Timing Optimization for Two-Terminal Interconnects
    1. 7.1. Interplane Interconnect Models
    2. 7.2. Two-Terminal Nets with a Single-Interplane Via
    3. 7.3. Two-Terminal Interconnects with Multiple-Interplane Vias
    4. 7.4. Summary
  15. Chapter 8. Timing Optimization for Multiterminal Interconnects
    1. 8.1. Timing-Driven Via Placement for Interplane Interconnect Trees
    2. 8.2. Multiterminal Interconnect Via Placement Heuristics
    3. 8.3. Via Placement Algorithms for Interconnect Trees
    4. 8.4. Via Placement Results and Discussion
    5. 8.5. Summary
  16. Chapter 9. 3-D Circuit Architectures
    1. 9.1. Classification of Wire-Limited 3-D Circuits
    2. 9.2. Three-Dimensional Microprocessors and Memories
    3. 9.3. Three-Dimensional Networks-on-Chip
    4. 9.4. Three-Dimensional FPGAs
    5. 9.5. Summary
  17. Chapter 10. Case Study
    1. 10.1. MIT Lincoln Laboratories 3-D IC Fabrication Technology
    2. 10.2. 3-D Circuit Architecture
    3. 10.3. Clock Signal Distribution in 3-D Circuits
    4. 10.4. Experimental Results
    5. 10.5. Summary
  18. Chapter 11. Conclusions
  19. Appendix A. Enumeration of Gate Pairs in a 3-D IC
  20. Appendix B. Formal Proof of Optimum Single Via Placement
  21. Appendix C. Proof of the Two-Terminal Via Placement Heuristic
  22. Appendix D. Proof of Condition for Via Placement of Multiterminal Nets
  23. Bibliography
    1. References
  24. Index
    1. SYMBOL
    2. A
    3. B
    4. C
    5. D
    6. E
    7. F
    8. G
    9. H
    10. I
    11. J
    12. K
    13. L
    14. M
    15. N
    16. O
    17. P
    18. R
    19. S
    20. T
    21. V
    22. W