The Unabridged Pentium 4 IA32 Processor Genealogy

An Intro to Level-Sensitive Interrupts

The later versions of the PCI spec permit device adapters to share the same IRQ signal line. The shareable IRQ signal lines are typically asserted when driven low and have a pull-up resistor on the system board that maintains the signal in the deasserted state when no devices are requesting service. An interrupt request is placed on the signal line by driving the signal low and the interrupt controller input (on the IO APIC) is programmed to recognize a static electrical low as a valid interrupt request. This is referred to as an active low, level-sensitive interrupt request. The interrupt controller (the IO APIC) sets the IRR bit associated with that input and forwards the request to the processor for servicing. ...