Miscellaneous
Hardware-Based Data Prefetcher
The Pentium® M processor has enhanced the hardware-based data prefetch logic (see “The Data Prefetcher” on page 747 for background). Public domain documentation does not document the nature of the improvements.
The L2 Cache
The Pentium® M processor includes an on-die 1MB L2 ATC capable of transferring data to the downstream requester (the L1 Data Cache or the Front-End instruction logic) in each core clock cycle. Its features include the following:
It is a non-blocking, full speed, on-die L2 cache.
It is organized as an 8-way set associative cache.
Data can be clocked into and out of the cache in every clock cycle.
Its access latency is five clock cycles.
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