Miscellaneous New Instructions
General
The 130nm Pentium® 4 processor added 144 new instructions to the IA32 instruction repertoire. This is referred to as the SSE2 instruction set. Of these, the author has chosen to discuss the following instructions separately in this section and the remainder are covered in “The SSE2 Instruction Set” on page 1332.
The CLFLUSH instruction is covered in “The Cache Line Flush Instruction” on page 1326.
The MFENCE instruction is covered in “The Memory Fence Instruction” on page 1326.
The LFENCE instruction is covered in “The Load Fence Instruction” on page 1326.
The non-temporal store instructions (also referred to as Streaming Stores) are covered in “The Non-Temporal Store Instructions” on page 1327.
The PAUSE instruction ...
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