The Unabridged Pentium 4 IA32 Processor Genealogy

Possible Solutions

The designers of the Root Complex can take one of three possible approaches:

1. The Root Complex could keep the FSB Data Bus busy for extensive periods of time. This is certainly the least-desirable approach.

2. The Root Complex can memorize the transaction and issue a retry response to the processor. This obligates the processor to re-arbitrate for ownership of the Request Phase signal group and retry the transaction on a periodic basis until it gets a good response and the read or write completes. When the Root Complex has finally completed the requested transaction on the PCI Express side, it waits for the processor's next retry. When it latches a transaction issued on the FSB, it compares the agent ID and transaction ID to see ...