The Unabridged Pentium 4 IA32 Processor Genealogy

Chapter 42. The Pentium^® 4 Prescott

The Previous Chapter

This chapter provided a detailed description of load and store operations and included:

• The Memory Type Defines Load/Store Characteristics.

• The Load Buffers.

• Loads from Cacheable Memory.

• Loads Can Be Executed Out-of-Order.

• The L1 Data Cache Implements Squashing.

• Loads from Uncacheable Memory.

• The Definition of a Speculatively Executed Load.

• Replay.

• Loads and the Prefetch Instructions.

• The LFENCE Instruction.

• Store-to-Load Forwarding.

• Stores Are Handled by the Store Buffers.

• Stores to UC Memory.

• Stores to WC Memory.

• Stores to WP Memory.

• Stores to WT Memory.

• Forcing a Buffer Drain.

• The SFENCE Instruction.

• Sharing Access to a UC, WC, WP or WT Memory Region.

• Stores to WB Memory.

• Out-of-Order String Stores.

• Stores ...