FSB Transactions and the Caches
Background
When the L1 Data Cache has a read miss, it forwards a request for the 64-byte cache line to the L2 Cache. If the L2 Cache has a read miss on the sector (i.e., half line) and there is no L3 cache, the fill request is passed to the FSB Interface Unit:
If the other sector of the target line is in the L2 Cache, a request for a single-sector read (i.e., a 64-byte read) is forwarded to the FSB Interface Unit.
If the other sector of the line is not in the L2 Cache, a request for a two-sector read (i.e., a 128-byte read) is forwarded to the FSB Interface Unit.
If the L2 Cache has a read miss and there is an L3 Cache, the fill request is passed to the L3 Cache for fulfillment. If the L3 has a miss on the sector ...
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