HT Cache-Related Issues
Whether a processor's caches are shared by the logical processors in a physical processor or they are replicated for each logical processor is implementation-specific. As of this writing (03/09/04), they are shared and, if any of the following cache management instructions are executed, the instruction operates upon all of the physical processor's caches:
WBINVD. All logical processors are stalled until all modified lines in the L2 and L3 Caches (the L1 Data Cache is a write-through cache and never contains modified lines) have been written back to system memory, after which all lines are deleted from all of the caches. The processor then performs the Special transaction on the FSB, outputting the Sync message on its ...
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