The Unabridged Pentium 4 IA32 Processor Genealogy

The Core Is Starving and Caching is Disabled

Reset's setting of the CR0[CD] and CR0[NW] bits to one disables the processor's ability to cache. Although this bit setting permits it to perform lookups in the caches, all lookups result in misses (because the caches were cleared by reset). This really is a moot point, because reset has caused the MTRRs to define all of memory space as UC (UnCacheable) memory. As a result, no cache lookups are performed for any memory accesses initiated by the processor core.

The instruction streaming buffer (i.e., the prefetch queue) and the entire instruction pipeline are empty, resulting in total starvation for the processor's fetch, decode and execute engine. The processor must therefore immediately begin fetching ...