The Unabridged Pentium 4 IA32 Processor Genealogy

Program-Accessible Startup Features

See Table 36-4 on page 870 and Figure 36-10 on page 872. The processor's MSR_EBC_HARD_POWERON (EBC stands for External Bus Controller; i.e., the FSB Controller) register is a read-only MSR that indicates the state of the automatic configuration options that were automatically enabled or disabled on the trailing-edge of reset (when the processor sampled a subset of its pins).

Figure 36-10. MSR_EBC_HARD_POWERON MSR

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Table 36-4. Bit Assignment of MSR_EBC_HARD_POWERON MSR Register

Bit	Read/Write	Description
0	RO	0 = Output Tri-state disabled. 1 = Output Tri-state Enabled. See “Tri-State Mode” on page ...