The Unabridged Pentium 4 IA32 Processor Genealogy

The L2 Cache

Refer to Figure 30-1 on page 747.

Figure 30-1. The L2 Cache Characteristics

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The L2 Cache on the Early Pentium® III

The earlier versions of the Pentium® III processor were implemented using the cartridge format and the L2 Cache was implemented using discrete SRAM chips (just as in the Pentium® II). The BSB ran at 50% of the processor core speed and the data bus portion of the BSB was 64-bits wide, permitting a single qword to be transferred per clock cycle from the L2 Cache to the L1 Cache. The L2 Cache had the following additional characteristics:

• It was a unified code/data cache.

• It was available in two versions, ...