The Unabridged Pentium 4 IA32 Processor Genealogy

The Sleep State

Refer to Figure 27-5 on page 693. The processor can only enter the Sleep state from the Stop Grant state. This occurs when the chipset asserts the SLP# (Sleep) signal to the processor while the processor is in the Stop Grant state. Upon entering the Sleep state, the processor powers off much of its logic, including that necessary for:

• Snooping memory accesses initiated by other agents on the FSB.

• Latching interrupt events.

Figure 27-5. The Sleep State

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The Sleep state has the following characteristics:

• The processor maintains the contents of its registers and caches.

• The processor's PLL (Phase Locked Loop) continues ...