Time Stamp Counter
Starting with the Pentium®, all IA32 processors implement the 64-bit Time Stamp Counter (TSC) register (see Figure 21-8 on page 501). It is cleared to zero on the assertion of reset to the processor. Upon the deassertion of the reset input, the TSC is incremented once for each processor clock cycle.
Figure 21-8. The Time Stamp Counter (TSC) Register
Reading the TSC
The TSC can be read in either of two ways:
Privilege level 0 code can use the RDMSR instruction to read the TSC. The TSC's MSR address is 10h. The programmer sets ECX = 10h and executes the RDMSR instruction. The current contents of the TSC is loaded into EDX and ...
Get The Unabridged Pentium 4 IA32 Processor Genealogy now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
