Debug Extension
Refer to Figure 21-6 on page 497. Setting CR4[DE] = 1 has the following effects:
It enables the ability to set IO as well as memory access breakpoints using the processor's Debug register set. In DR7, the R/W fields associated with each of the four possible breakpoints are used as follows:
- 00b: Break on instruction execution only.
- 01b: Break on data writes only.
- 10b: Break on IO reads or writes. When CR4[DE] = 0, this pattern is reserved.
- 11b: Break on data reads or writes but not instruction fetches.
DR4 and DR5 are reserved and attempts to access DR4 and DR5 result in the generation of an Invalid Opcode exception. When CR4[DE] = 0, access attempts to DR4 and DR5 are aliased to DR6 and DR7, respectively.
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