An Overview of the 486 Internal Architecture
Figure 18-1 on page 414 illustrates the internal architecture of the 486 processor. It should be noted that the initial version of the 486 did not incorporate the FPU. The 486 processor core consisted of the following units:
Bus Unit. Interfaces the processor to the FSB and the system in general.
Instruction Prefetch Unit. Working on the presumption that the currently executing program never executes jumps, it instructs the Bus Unit to perform a series of memory code read transactions from ascending memory addresses.
Prefetch Queue (not shown). The instructions prefetched from memory are placed in this queue. The queue was 16 bytes deep on the 386 and was increased to 32 bytes on the 486.
Instruction ...
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