The Unabridged Pentium 4 IA32 Processor Genealogy

A Unified Cache

A unified cache is a cache that contains both code (instructions) and data. Figure 17-6 on page 409 represents a basic view of a P6 family processor. The L2 Cache is a unified code/data cache that services requests forwarded to it from both the L1 Data Cache and the L1 Code Cache.

Figure 17-6. P6 Family Processor

The disadvantage of a unified cache is this:

• If a request forwarded from the L1 Data Cache misses in the L2 Cache, the L2 Cache must fetch the data line from memory. When the data line is returned from memory, the L2 Cache uses its LRU algorithm to decide where to place the new line. This may cause the castout of a code ...