The Unabridged Pentium 4 IA32 Processor Genealogy

Special Case—Interrupts Disabled While Updating SS:ESP

The Problem

Assume that the programmer executes the following code to switch to a different stack:

mov ss,ax         ;move new value into ss
mov esp, stacktop ;move new top-of-stack offset into esp

Now assume that the processor is interrupted after execution of the first move but before the second begins execution. When the processor pushes the CS, EIP and EFlags values onto the stack, it will be using the new stack segment descriptor to obtain the stack base address and the old ESP value—in other words, you've got a mess on your hands.

The Solution

To prevent this problem, IA32 processors automatically inhibit recognition of interrupts and debug exceptions after either a move to SS or a pop to ...